1. Field of the Invention
The present invention relates in general to a semiconductor device and a method of manufacturing the same, and in particular to a semiconductor device formed on an insulating layer and a method of manufacturing the same.
2. Description of the Background Art
In order to improve the performance of semiconductor devices, there have been developed semiconductor devices in which circuit elements are isolated by dielectrics and a floating capacitance is small. For forming transistors on a thin silicon film on an insulating film, which will be referred to as an SOI (Silicon On Insulation) layer, an MESA isolating method is used for isolating the transistors from each other. According to this MESA isolating method, the isolated transistors are formed at completely isolated or insular SOI layers, respectively. This brings about many advantages such as prevention of influence of latch-up between adjacent transistors.
FIGS. 198 to 206 are cross sections showing a process of manufacturing an SOI-MOSFET using a conventional MESA isolating method. Referring to FIG. 206, description will be given on a structure of the SOI-MOSFET formed by the conventional MESA solating method. In this SOI-MOSFET, a buried oxide film 2 is formed on a silicon substrate 1. SOI layers 3 are formed at predetermined regions on buried oxide film 2 with a predetermined space between each other. Silicon substrate 1, buried oxide film 2 and SOI layers 3 form an SOI substrate. Source/drain regions 3e and 3f having an LDD structure are formed on SOI layer 3 at an PMOS region with a predetermined space between each other and are located at opposite sides of a channel region 3g. Titanium silicide films 8a are formed on the surfaces of source/drain regions 3e and 3f. A gate electrode 6 is formed on channel region 3g with a gate oxide film 5 therebetween. Titanium silicide film 8a is also formed also on the upper surface of gate electrode 6. Side wall oxide films 13 are formed in contact with side surfaces of gate electrode 6.
On SOI layer 3 at an NMOS region, there are formed source/drain regions 3b and 3c having an LDD structure with a predetermined space between each other and are located at opposite sides of a channel region 3d. A gate electrode 6 is formed on channel region 3d with a gate oxide film 50 therebetween. Side wall oxide films 13 are formed in contact with side surfaces of gate electrode 6. Titanium silicide films 8a are formed on source/drain regions 3b and 3c and gate electrode 6. The PMOS and NMOS regions are covered with an interlayer oxide film 9. Contact holes are formed at regions of interlayer oxide film 9 located above source/drain regions 3b, 3c, 3e and 3f. There are provided metal interconnection layers 10 having portions filling the contact holes. Gate electrodes 6 are formed of polycrystalline silicon films containing phosphorus (P) at 1xc3x971020/cm2 or more. Titanium silicide films 8a are formed for reducing resistances of source/drain regions 3b, 3c, 3e and 3f and gate electrode 6.
Referring to FIGS. 198 to 206, a process of manufacturing the SOI-MOSFET using the conventional MESA isolating method will be described below.
As shown in FIG. 198, buried oxide film 2 is first formed on silicon substrate 1. After forming SOI layer 3 on buried oxide film 2, a surface of SOI layer 3 is oxidized to form oxide film 5 having a thickness from about 100 xc3x85 to about 200 xc3x85. A resist 201 is formed at predetermined regions on oxide film 5. Using resist 201 as a mask, dry etching is effected on oxide film 5 and SOI layer 3. Thereby, SOI layers 3 forming active regions of transistors spaced by a predetermined distance are formed as shown in FIG. 199.
In this isolating method, predetermined regions of SOI layer 3 are removed by the etching to break electrical connection between adjacent transistors, which is called the MESA isolating method. Thereafter, resist 201 is removed. A resist 202 is formed to cover the PMOS region. Using resist 202 as a mask, boron ions are implanted into SOI layer 3 at the NMOS region under the conditions of 20 keV and 1xc3x971012-3xc3x971012/cm2. This implantation is performed for forming the channel region of NMOSFET. Thereafter, resist 202 is removed.
As shown in FIG. 200, a resist 203 is then formed over the NMOS region. Using resist 203 as a mask, phosphorus ions are implanted into SOI layer 3 at the PMOS region under the conditions of 30 kev and 1xc3x971011-3xc3x971011/cm2. This implantation is performed for forming the channel region of the PMOSFET. Thereafter, resist 203 is removed. Oxide film 5 on SOI layer 3 is removed.
As shown in FIG. 201, gate oxide film 50 having a thickness of about 100 xc3x85 is formed over each SOI layer 3. Polycrystalline silicon layer 6 containing phosphorus at 1xc3x971020/cm2 or more and having a thickness of about 2000 xc3x85 is formed over gate oxide films 50 and buried oxide film 2. A resist 204 is formed at predetermined regions on polycrystalline silicon layer 6. Using resist 204 as a mask, dry etching is effected on polycrystalline silicon layer 6 to form gate electrodes 6 as shown in FIG. 202. After removing resist 204 (shown in FIG. 201), a resist 205 is formed over the PMOS region. Using resist 205 and gate electrodes 6 at the NMOS region as a mask, phosphorus ions are implanted into SOI layer 3 at the NMOS region under the conditions of 40 keV and 1xc3x971013-3xc3x971013/cm2. This implantation is performed for forming a lightly doped region in the LDD structure. Thereafter, resist 205 is removed.
As shown in FIG. 203, a resist 206 is formed over the NMOS region. Using resist 206 as a mask, boron ions are implanted into SOI layer 3 at the PMOS region under the conditions of 20 keV and 1xc3x971013-3xc3x971013/cm2. This implantation is performed for forming a lightly doped region forming the LDD structure of the PMOSFET. Thereafter, resist 206 is removed.
As shown in FIG. 204, side wall insulating films 13 are formed in contact with side surfaces of gate electrode 6. Side wall insulating films 13 may be formed by effecting anisotropic etching on an insulating film (now shown) which was formed over gate electrode 6. Thereafter, a resist 207 is formed over the PMOS region. Using resist 207, gate electrode 6 at the NMOS region and side wall insulating films 13 as a mask, phosphorus ions are implanted into SOI layer 3 at the NMOS region under the conditions of 40 keV and 4xc3x971015-6xc3x971015/cm2. This implantation is performed for forming heavily doped regions forming the source/drain regions in the NMOSFET. Thereafter, resist 207 is removed. Arsenic may be used as implanted ion species for the source/drain regions.
As shown in FIG. 205, a resist 208 is formed over the NMOS region. Using resist 208, gate electrode 6 at the PMOS region and side wall insulating films 13 as a mask, boron ions are implanted into SOI layer 3 at the PMOS region under the conditions of 20 keV and 4xc3x971015-6xc3x971015/cm2. This implantation is performed for forming heavily doped regions forming the source/drain regions in the PMOSFET. Thereby, source/drain regions 3e and 3f having the LDD structure are formed. Thereafter, resist 208 is removed.
Then, as shown in FIG. 206, titanium silicide layers 8a are formed on the surfaces of source/drain regions 3b, 3c, 3e and 3f and gate electrodes 6. After forming interlayer insulating film 9 of about 7000 xc3x85 in thickness over the whole surface, the contact holes are formed at regions located above source/drain regions 3b, 3c, 3e and 3f. The aluminum layer having portions filling the contact holes is formed and then is patterned to form metal interconnection layers 10. In this manner, the SOI-CMOSFETs isolated by the conventional MESA isolating method are completed as shown in FIG. 206.
However, in the conventional semiconductor device thus constructed, a parasitic transistor is formed at a region where gate electrode 6 and SOI layer 3 overlap with each other, and in particular at a region near the side surface of SOI layer 3. FIG. 207 is a cross section taken along line perpendicular to the section shown in FIG. 206. Referring to FIG. 207, an electric field concentrates at an upper end of SOI layer 3 where the parasitic transistor is formed, and an interface level is formed at the upper end due to the process. Therefore, a disadvantage occurs in connection with subthreshold characteristics of a regular MOS transistor formed at SOI layer 3. More specifically, since the threshold voltage of parasitic transistor lowers as already described, such a disadvantage is caused that the parasitic transistor is turned on by a voltage lower than the threshold voltage of the regular transistor. This and other disadvantages are specifically disclosed in xe2x80x9cELECTRONICS LETTERS 18th, Augustxe2x80x9d, Vol. 19, No. 17, 1983, pp. 684-685.
In order to overcome the above-noted problem, there have been proposed manufacturing processes for preventing concentration of electric field at the upper end of SOI layer 3. These are disclosed, for example, in U.S. Pat. No. 4,753,896. FIGS. 208 to 214 are cross sections showing the proposed manufacturing process. Referring to FIGS. 208 to 214, the proposed manufacturing process will be described below.
As shown in FIG. 208, buried insulating film 2 is first formed on semiconductor substrate 1. SOI layer 3 is formed on buried insulating film 2. A nitride film 4a is formed at a predetermined region of SOI layer 3 with oxide film 5 therebetween. Using nitride film 4a as a mask, impurity is ion-implanted into SOI layer 3. This ion implantation is performed for raising a threshold voltage of a parasitic transistor.
As shown in FIG. 209, side wall nitride film 4b is then formed in contact with side surfaces of nitride film 4a and oxide film 5. Using side wall nitride film 4b and nitride film 4a as a mask, dry etching is effected on SOI layer 3 to form patterned SOI layer 3 shown in FIG. 210.
As shown in FIG. 211, an oxide film 120 is formed to cover nitride film 4a, side wall nitride film 4b, SOI layer 3 and buried oxide film 2. Anisotropic etching is effected on oxide film 120 to form side wall oxide films 120 as shown in FIG. 213. Thereafter, nitride film 4a, side wall nitride film 4b and oxide film 5 are removed. As shown in FIG. 214, gate oxide film 50 is formed over SOI layer 3 and side wall oxide film 120, and then gate electrode 6 is formed on gate oxide film 50. In the structure thus formed, since side wall oxide film 120 is interposed between the side surface of SOI layer 3 and gate electrode 6, a portion of the parasitic transistor corresponding to a gate oxide film has a large thickness, so that an electric field applied from gate electrode 6 in the parasitic transistor is weaken. Consequently, the subthreshold characteristics of regular transistor is prevented from being affected by the characteristics of the parasitic transistor.
However, the proposed manufacturing process may suffer from the following problem. FIGS. 215 to 217 are cross sections showing the problem of the proposed manufacturing process. In the proposed manufacturing process, heat treatment is performed to activate the impurity implanted into SOI layer 3 after forming oxide film 120 at the step shown in FIG. 212. During this heat treatment, oxidant moves up to the bottom and upper surfaces of the side portion of SOI layer 3 as shown in FIG. 215. Thereby, the side portion of SOI layer 3 is shaped into an acute form. In this state, the side wall oxide film 120 is formed as shown in FIG. 216, and then gate oxide film 50 and gate electrode 6 are formed. In this case, an electric field concentrates at the side portion of SOI layer 3. As a result, the threshold voltage of parasitic transistor lowers, and thus the parasitic transistor tends to be turned on. Thereby, the subthreshold characteristics of regular transistor are adversely affected.
In the process of forming side wall oxide film 120 shown in FIGS. 212 and 213, it is necessary to perform over-etching on oxide film 120 for completely removing oxide film 120 on nitride film 4a when performing the anisotropic etching on oxide film 120. As a result of this over-etching, side wall oxide film 120 is formed not to cover the upper portion of side surface of SOI layer 3 as shown in FIG. 219. Gate oxide film 50 and gate electrode 6 are formed over this structure as shown in FIG. 219, whereby the electric field disadvantageously concentrates at the upper side end of SOI layer 3. This lowers the threshold voltage of parasitic transistor, and thus the subthreshold characteristics of regular transistor are adversely affected. As described above, various problems arise in the manufacturing process proposed in the prior art, and consequently, it is difficult to improve the subthreshold characteristics of regular transistor.
An object of the invention is to provide a semiconductor device which is not affected by a parasitic transistor.
Another object of the invention is to provide a semiconductor device which can prevent concentration of an electric field at the vicinity of a side surface of an SOI layer.
Still another object of the invention is to provide a method which can easily manufacture a semiconductor device not affected by a parasitic transistor without complicating a manufacturing process.
A semiconductor device according to an aspect of the invention includes a semiconductor layer and a field-effect transistor. The semiconductor layer is formed at a predetermined region of an insulating layer, and has a main surface. The field-effect transistor is formed on the main surface of the semiconductor layer. The semiconductor layer has a round section at an upper portion of its side surface, and the insulating layer has a U-shaped concavity at a region located near a lower end of the side surface of the semiconductor layer. Preferably, the lower end of the side surface of the semiconductor layer may extend substantially perpendicularly to the main surface of the insulating layer, and an open end of the concavity of the insulating layer may extend continuously to the lower end of the side surface of the semiconductor layer. Preferably, a first side wall insulating film may be further formed in contact with the side surface of the semiconductor layer, and a second side wall insulating film may be formed in contact with a side surface of the first side wall insulating film.
According to the semiconductor device described above, since the upper side portion of the semiconductor layer located on the insulating layer has a round section, it is possible to prevent concentration of an electric filed at the upper side portion of the semiconductor layer. Thereby, lowering of a threshold voltage of a parasitic transistor is prevented. Since the insulating layer has the U-shaped concavity at the region located near the lower end of the side surface of the semiconductor layer, etching residue is prevented from remaining at the vicinity of the lower end of the side surface of the semiconductor layer when patterning a gate electrode layer at a later step. If the first side wall insulating film is provided in contact with the side surface of the semiconductor layer and the second side wall insulating film is provided in contact with the side surface of the first side wall insulating film, the first and second side wall insulating films are interposed between the side surface of the semiconductor layer and the gate electrode, which weakens an influence by an electric field applied from the gate electrode to the side surface of semiconductor layer. Thereby, the threshold voltage of the parasitic transistor increases.
A semiconductor device according to another aspect of the invention includes an insulating layer, a semiconductor layer, an oxide film, a first field-effect transistor and a nitride film. The insulating layer is patterned to have an isolated or insular form, and has a main surface. The semiconductor layer is formed on the main surface of the insulating layer. The oxide film is formed in contact with at least a side surface of the semiconductor layer. The first field-effect transistor is formed on the main surface of the semiconductor layer. The nitride film is formed in contact with a side surface of the insulating layer and a lower portion of the oxide film located at the side surface of the semiconductor layer. Preferably, the insulating layer may include first and second insulating layers spaced by a predetermined distance, the semiconductor layer may include first and second semiconductor layers formed on main surfaces of the first and second insulating layers, respectively, the nitride film may include a first nitride film formed in contact with a side surface of the first insulating layer and a lower portion of a side surface of the first semiconductor layer, a second nitride film formed in contact with a side surface of the second insulating layer and a lower portion of the side surface of the second semiconductor layer, and an oxide film may be buried between the first and second nitride films. More preferably, the nitride film may be buried such that the first insulating layer and the first semiconductor layer are opposed to the second insulating layer and the second semiconductor layer with the nitride film therebetween. Preferably, the side surface of the semiconductor layer may have a round section at its upper end. Preferably, the patterned insulating layer may be formed on a main surface of a semiconductor substrate, and a second field-effect transistor neighboring to the insulating layer may be formed at the main surface of the semiconductor substrate.
According to the semiconductor device of the above aspect, the nitride film is formed in contact with the side surface of the patterned and isolated insulating layer and the lower portion of the oxide film located at the side surface of the semiconductor layer formed on the insulating layer, so that oxidant is prevented from moving or flowing up to the lower surface of the semiconductor layer when oxidizing the side surface of the semiconductor layer damaged by etching during the patterning. Thereby, the rear surface of the semiconductor layer is not oxidized, and thus a stress is prevented from being applied to the semiconductor layer. The oxide film may be buried between the first nitride film, which is formed in contact with the side surface of the first insulating layer and the lower portion of the side surface of the first semiconductor layer, and the second nitride film, which is formed on the side surface of the second insulating layer and the lower portion of the side surface of the second semiconductor layer, whereby a difference in level or height is reduced, and a parasitic capacitance is reduced. The nitride film may be buried such that the first insulating layer and the first semiconductor layer formed thereon are opposed to the second insulating layer and the second semiconductor layer formed thereon with the nitride film therebetween, whereby a difference in level or height is reduced. The upper end portion of the side surface of the semiconductor layer may have a round section, which prevents concentration of an electric field at the upper end portion of the side surface of the semiconductor layer, so that lowering of the threshold voltage of a parasitic transistor is prevented. If the patterned insulating layer is formed on the main surface of the semiconductor substrate, and the second field-effect transistor neighboring to the insulating layer is formed on the main surface of the semiconductor substrate, the first and second field-effect transistors can be formed without leaving a space therebetween, so that the semiconductor device can be integrated to a higher extent.
A semiconductor device according to still another aspect of the invention includes a semiconductor layer and a field-effect transistor. The semiconductor layer is formed at a predetermined region on the insulating layer, has a main surface, is of a trapezoidal section, and has a round section at an upper portion of its side surface. The field-effect transistor is formed at the main surface of the semiconductor layer.
According to the above structure, concentration of an electric field at the upper side portion of the semiconductor layer can be suppressed as compared with the case where the semiconductor layer has a square section.
A semiconductor device according to yet another aspect of the invention includes semiconductor layers, a gate insulating film and a nitride film. The semiconductor layers are formed on an insulating layer, are located at a plurality of positions with a predetermined space between each other, and having main surfaces. The gate insulating film is formed in contact with upper surfaces and side surfaces of the semiconductor layers. The nitride film is formed to cover portions of the gate insulating film located on the side surfaces of the semiconductor layers and upper surfaces of portions of the insulating layer located between the semiconductor layers adjacent to each other.
According to the above structure, it is possible to prevent movement of oxidant up to lower surfaces of the semiconductor layers when oxidizing the upper portions of the side surfaces of the semiconductor layers. Thereby, a stress is prevented from being applied to the lower surfaces of the semiconductor layers.
A semiconductor layer according to a further aspect of the invention includes semiconductor layers, a concavity, side wall insulating films and a polycrystalline silicon layer. The semiconductor layers are formed on an insulating layer with a predetermined space between each other, and have main surfaces. The concavity is formed at a region of a main surface of the insulating layer located under a side end of the semiconductor layer. The side wall insulating films are in contact with the side surfaces of the semiconductor layers and have portions filling the concavity. The polycrystalline silicon layer is buried at an isolating region between the adjacent semiconductor layers.
According to the semiconductor device of this aspect, since the side wall insulating films formed on the side surfaces of the semiconductor layers fill the concavity at the insulating layer, an influence by an electric field applied from a gate electrode to the side surface of the semiconductor layer is weakened. Thereby, a threshold voltage of a parasitic transistor increases. Since the polycrystalline silicon layer is buried at the isolating region between the adjacent semiconductor layers, the isolating region is flattened. Since the polycrystalline silicon layer has the same thermal expansion coefficient as the semiconductor layer, a thermal stress is effectively suppressed in the structure.
A semiconductor device according to a further aspect of the invention includes an insulating layer, a semiconductor layer and an oxide film. The insulating layer has a convexity at a predetermined region. The semiconductor layer is formed on an upper surface of the convexity and has a portion at its lower surface supported by the convexity. The oxide film is interposed between the upper surface of the convexity and the semiconductor layer.
The above structure prevents generation of fixed electric charges at an interface between the insulating layer and the semiconductor layer.
According to a method of manufacturing a semiconductor device of an aspect of the invention, a nitride film is formed at a predetermined region on a main surface of a first semiconductor layer located on an insulating layer. A side wall insulating film is formed in contact with a side surface of the nitride film. The first semiconductor layer is etched to pattern the first semiconductor layer using the nitride film and the side wall insulating film as a mask. A second semiconductor layer covering at least the insulating layer, the first semiconductor layer and the nitride film is formed. The second semiconductor layer is oxidized to form an oxide film.
The above method can prevent movement of oxidant up to a lower surface of the first semiconductor layer through the insulating layer when oxidizing the second semiconductor layer. Meanwhile, since the oxidant moves onto the upper portion of the side surface of the first semiconductor layer, the upper side portion is oxidized to have a round section. Thereby, it is possible to prevent concentration of an electric field at the upper side portion of the first semiconductor layer, and the semiconductor device which can prevent a stress at the lower surface of the first semiconductor layer can be easily manufactured.
According to a method of manufacturing a semiconductor device of a further aspect of the invention, a nitride film is formed at a predetermined region on a main surface of a semiconductor layer located on an insulating layer, and a side wall insulating film is formed in contact with a side surface of the nitride film. Etching is effected on the semiconductor layer to remove a predetermined thickness using the nitride film and the side wall insulating film as a mask. The semiconductor layer is selectively oxidized to form an oxide film using the nitride film as a mask.
The above method can easily form the semiconductor layer of such a form that an upper portion of its side surface has a round section and a lower portion of the side surface is substantially perpendicular to the insulating layer.
According to a method of manufacturing a semiconductor device of a further aspect of the invention, a nitride film is formed at a predetermined region on a main surface of a semiconductor layer, and the semiconductor layer is selectively oxidized to form an oxide film using the nitride film as a mask. At least a region of the nitride film near its side surface is removed by the etching, and anisotropic etching is effected on the oxide film and the semiconductor layer using the nitride film as a mask.
Thereby, the semiconductor layer has such a form that an upper portion of its side surface has a round section and a lower portion of the side surface is substantially perpendicular to a main surface of the insulating layer. Therefore, the method can easily manufacture the semiconductor device not affected by a parasitic transistor.
According to the method of manufacturing a semiconductor device of a further aspect, after forming a nitride film at a predetermined region on a main surface of a first semiconductor layer, the first semiconductor layer is isotropically etched using the nitride film as a mask for removing a portion of the first semiconductor layer not located under the nitride film and a portion of the first semiconductor layer located under a side surface of the nitride film. A second semiconductor layer is formed by a sputtering method to cover the nitride film, the first semiconductor layer and the insulating layer. The second semiconductor layer is oxidized.
The above method provides the second semiconductor layer of which portion located on a side surface of the first semiconductor layer is thinner than the other portion. This promotes oxidation of the side portion of the first semiconductor layer, which was damaged during the etching, when oxidizing the second semiconductor layer.
According to a method of manufacturing a semiconductor device of a further aspect of the invention, a resist film is formed at a predetermined region on a main surface of a first semiconductor layer located on an insulating layer. Etching is effected on the first semiconductor layer to pattern the first semiconductor layer using the resist film as a mask. Impurity is ion-implanted into a side surface of the first semiconductor layer using the resist film as a mask. After removing the resist film, a sputtering method is performed to form a second semiconductor layer covering the first semiconductor layer and the insulating layer. The second semiconductor layer is oxidized.
This method provides the semiconductor layer of which portion located on a side surface of the first semiconductor layer is thinner than the other portion. This promotes oxidation of the side portion of the first semiconductor layer, which was damaged during the etching, when oxidizing the second semiconductor layer.
According to a method of manufacturing a semiconductor device of a further aspect of the invention, a nitride film is formed at a predetermined region on a main surface of a first semiconductor layer located on an insulating layer. A side wall oxide film is formed in contact with a side surface of the nitride film. The first semiconductor layer is etched to pattern the first semiconductor layer using the nitride film and the side wall oxide film as a mask. After removing the side wall oxide film, inactive ions are implanted into the first semiconductor layer using the nitride film as a mask. Thereafter, heat treatment is performed. The first semiconductor layer is oxidized to form an oxide film using the nitride film as a mask. Impurity ions are implanted into the side surface of the first semiconductor layer through the oxide film.
According to the method of manufacturing the semiconductor device of the above aspect, since the heat treatment is performed after the inactive ions are implanted into the first semiconductor layer using the nitride film as a mask, metal contaminant in the semiconductor layer is gathered into a region into which inactive ions were implanted. By oxidizing the first semiconductor layer, the metal contaminant is taken into the oxide film which is formed by oxidizing the first semiconductor layer. Thereby, the metal contaminant is prevented from remaining at the vicinity of a side surface of the first semiconductor layer.
According to a method of manufacturing a semiconductor device of a further aspect of the invention, a nitride film is formed on a main surface of a first semiconductor layer, and a resist film is formed at a predetermined region on the nitride film. Inactive ions and impurity ions are implanted into a region near a side surface of the first semiconductor layer using the resist film as a mask. A second semiconductor layer is formed to cover the nitride film, the first semiconductor layer and the insulating layer. A region near the side surface of the first semiconductor layer and the second semiconductor layer are oxidized.
Thereby, metal contaminant is absorbed into an oxide film formed by oxidation, and a threshold voltage at the region near the side surface of the first semiconductor layer rises.
According to a method of manufacturing a semiconductor device of a further aspect of the invention, a nitride film is formed at a predetermined region on a main surface of a semiconductor layer, and the semiconductor layer is selectively oxidized over a predetermined thickness to form a first oxide film using the nitride film as a mask. After removing the first oxide film, the semiconductor layer is oxidized over a remaining thickness to form a second oxide film using the nitride film as a mask.
Thereby, a side surface of the semiconductor layer has a round section at and near its upper portion, and also has a lower portion extending substantially perpendicularly to a main surface of the insulating layer. This prevents formation of a region of the semiconductor layer having a reduced thickness near the side surface of the semiconductor layer.
According to a method of manufacturing a semiconductor device of a further aspect of the invention, a nitride film is formed at a predetermined region on a main surface of a semiconductor layer located on an insulating layer. The semiconductor layer is etched to pattern the semiconductor layer using the nitride film as a mask. A side portion of the semiconductor layer is oxidized using the nitride film as a mask. At least a portion of the nitride film located near the side surface of the semiconductor layer is removed. Impurity ions are implanted into a portion near the side surface of the semiconductor layer using the nitride film as a mask.
This allows easy formation of an impurity implanted layer, which serves to raise a threshold voltage of a parasitic transistor, at the vicinity of the side surface of the semiconductor layer.
According to a method of manufacturing a semiconductor device of a further aspect of the invention, a nitride film is formed at a predetermined region on a main surface of a semiconductor layer located on an insulating layer. Then, the semiconductor layer is selectively oxidized to form a first oxide film using the nitride film as a mask. After removing the first oxide film by etching, a side portion of the semiconductor layer is oxidized to form a second oxide film using the nitride film as a mask.
According to the method of manufacturing the semiconductor device of the above aspect, the nitride film formed at the predetermined region on the main surface of the semiconductor layer is used as a mask, and the semiconductor layer is selectively oxidized to form the first oxide film. At this stage, a lower portion of the side surface of the semiconductor layer has an acute form. Thereafter, the side portion of the semiconductor layer is oxidized using the nitride film as a mask. During this oxidation, the acute portion is oxidized prior to oxidation of the other portion, so that the semiconductor layer ultimately has the side portion of a round section.
According to a method of manufacturing a semiconductor device of a further aspect of the invention, a nitride film is formed at a predetermined region on a main surface of a semiconductor layer located on an insulating layer. The semiconductor layer is selectively oxidized over a predetermined thickness to form a first oxide film using the nitride film as a mask. The first oxide film is etched and removed using the nitride film as a mask. A side wall nitride film is formed in contact with a side surface of the nitride film. A predetermined portion of the semiconductor layer is anisotropically etched and removed using the side wall nitride film as a mask. A side surface of the semiconductor layer is oxidized to form a second oxide film.
According to the method of manufacturing the semiconductor device of the above aspect, since the first oxide film is formed by selectively oxidizing the semiconductor layer over a predetermined thickness using the nitride film as a mask, an upper side portion of the semiconductor layer located at a boundary region between the semiconductor layer and the first oxide film is rounded when forming the first oxide film. This suppresses concentration of an electric field applied from a gate electrode to the upper side portion of the semiconductor layer in the completed structure. After forming the side wall nitride film on the side surface of the nitride film, a predetermined portion of the semiconductor layer is removed using the side wall nitride film as a mask, so that the produced semiconductor layer has a thickness larger than the originally designed size by a value corresponding to a thickness of the side wall nitride film. Therefore, an effective channel width is not reduced by oxidation of the side surface of the semiconductor layer.
According to a method of manufacturing a semiconductor device of a further aspect of the invention, a semiconductor layer having a main surface is formed on an insulating layer, and then an oxide film is formed on the main surface of the semiconductor layer. A nitride film is formed on the oxide film. A side wall nitride film being in contact with a side surface of the nitride film is formed on the oxide film. The semiconductor layer is etched into an isolated or insular form using the nitride film and the side wall nitride film as a mask. A side surface of the semiconductor layer is oxidized to form a side wall oxide film using the nitride film and the side wall nitride film as a mask. The nitride film and the side wall nitride film are removed with thermo-phosphoric acid.
According to the method of manufacturing the semiconductor device of the above aspect, since the nitride film and the side wall nitride film are formed on the oxide film formed on the main surface of the semiconductor layer, the oxide film located under the nitride film and the side wall nitride film serves as a protective film for the semiconductor layer when removing the nitride film and the side wall nitride film with the thermo-phosphoric acid. Thereby, the upper surface of the semiconductor layer is prevented from being etched by the thermo-phosphoric acid when removing the side wall nitride film.
According to a method of manufacturing a semiconductor device of a further aspect of the invention, a second semiconductor layer is formed on a main surface of a first semiconductor layer located on an insulating layer. A nitride film is formed at a predetermined region on a main surface of the second semiconductor layer. The second semiconductor layer is selectively oxidized to give a trapezoidal section to the second semiconductor layer using the nitride film as a mask. The second and first semiconductor layers are anisotropically etched to remove the second semiconductor layer and give a trapezoidal section to the first semiconductor layer.
This method can easily manufacture the semiconductor device which can suppress concentration of an electric field.
According to a method of manufacturing a semiconductor device of a further aspect of the invention, a plurality of isolated semiconductor layers are formed on an insulating layer with a predetermined space between each other. A nitride film is formed to cover an upper surface of the insulating layer located at an isolation region between the adjacent semiconductor layers as well as a side surface of the semiconductor layer. An upper side portion of the semiconductor layer is oxidized using the nitride film as a mask.
The method can effectively prevent movement of oxidant up to a lower surface of the semiconductor layer when oxidizing the upper side portion of the semiconductor layer.
According to a method of manufacturing a semiconductor device of a further aspect of the invention, a plurality of isolated semiconductor layers are formed on a main surface of an insulating layer with a predetermined space between each other. A concavity is formed at a region of the insulating layer located between the isolated semiconductor layers and near a lower side portion of the semiconductor layer. A side wall insulating film filling the concavity at the lower side portion of the semiconductor layer is formed in contact with the side surface of the semiconductor layer. A polycrystalline silicon layer filling the concavity between the adjacent semiconductor layers is formed.
This method can easily form a structure in which the isolating region is flattened.
According to a method of manufacturing a semiconductor device of a further aspect of the invention, a semiconductor layer is formed on a first insulating layer. A second insulating layer is formed at a region on a main surface of the semiconductor layer corresponding to an isolation region. An epitaxial growth layer having a trapezoidal section is formed by epitaxial growth from an exposed surface of the semiconductor layer using the second insulating layer as a mask. After removing the second insulating layer, anisotropic etching is effected on the epitaxial growth layer and the semiconductor layer to form a plurality of isolated semiconductor layers each having a trapezoidal section.
This method can easily manufacture the semiconductor device which suppresses concentration of an electric field.
According to a method of manufacturing a semiconductor device of a further aspect of the invention, a semiconductor layer is formed at a predetermined region on a main surface of an insulating layer. The insulating layer is isotropically etched, using the semiconductor layer as a mask, to remove a portion of the insulating layer,in contact with a lower surface of the semiconductor layer by a predetermined amount. The semiconductor layer is oxidized to form an oxide film at least between the lower surface of the semiconductor layer and the insulating layer.
The above method prevents generation of fixed charges between the insulating layer and the semiconductor layer.
According to a method of manufacturing a semiconductor device of a further aspect of the invention, a nitride film is formed at a predetermined region on a main surface of a semiconductor layer located at a predetermined region on an insulating layer. The semiconductor layer is selectively oxidized to form an element isolating oxide film using the nitride film as a mask. Impurity is ion-implanted into a side end of the semiconductor layer through the element isolating oxide film using the nitride film as a mask.
This method prevents such a disadvantage that impurity implanted into the side end of the semiconductor layer is absorbed when forming the element isolating oxide film. Thereby, lowering of a threshold voltage of a parasitic transistor is prevented.
According to a method of manufacturing a semiconductor device of a further aspect of the invention, a nitride film is formed at a predetermined region on a main surface of a semiconductor layer located on an insulating layer. The semiconductor layer is etched to pattern the semiconductor layer into a plurality of isolated forms using the nitride film as a mask. A side surface of the semiconductor layer is oxidized to form a side wall oxide film using the nitride film as a mask. Impurity is ion-implanted into a portion of the semiconductor layer near its side surface through the side wall oxide film using the nitride film as a mask.
This method prevents such a disadvantage that impurity implanted into the portion of the semiconductor layer near the side surface is absorbed when forming the side wall oxide film. Thereby, lowering of a threshold voltage of a parasitic transistor is prevented.
According to a method of manufacturing a semiconductor device of a further aspect of the invention, a semiconductor layer is formed on an insulating layer, and the semiconductor layer and the insulating layer are patterned into a predetermined form. A nitride film is formed in contact with a side surface of the insulating layer and a lower portion of a side surface of the semiconductor layer. The side surface of the semiconductor layer is oxidized using the nitride film as a mask. Preferably, the step of oxidizing the side surface of the semiconductor layer may be performed in a wet atmosphere under a temperature condition not lower than 1100xc2x0 C. Preferably, CMP (Chemical-Mechanical Polishing) may be effected on an upper portion of the side surface of the semiconductor layer prior to the step of oxidizing the side surface of the semiconductor layer, such that the upper portion of the side surface may be rounded. Preferably, the semiconductor layer and the insulating layer may be patterned to form a first insulating layer and a first semiconductor layer located on the first insulating layer as well as a second insulating layer spaced from the first insulating layer by a predetermined distance and the second semiconductor layer located on the second insulating layer, formation of the nitride film is performed such that a first nitride film is formed in contact with a side surface of the first insulating layer and a lower portion of a side surface of the first semiconductor layer and a second nitride film is formed in contact with a side surface of a second insulating layer and a lower portion of a side surface of a second semiconductor layer, and an oxide film may be formed to fill a space between the first and second nitride films.
According to the method of manufacturing the semiconductor device of the above aspect, the nitride film is formed in contact with the side surface of the insulating layer and the lower portion of the side surface of the semiconductor layer, and then the side surface of the semiconductor layer is oxidized using the nitride film as a mask, so that oxidant is prevented from moving to a space between the semiconductor layer and the insulating layer during oxidation of the side surface of the semiconductor layer. Thereby, a stress applied to a rear surface of the semiconductor layer is prevented. As a result, a leak current which may be caused by the stress is prevented. If the oxidation of the side surface of the semiconductor layer is performed in the wet atmosphere under the temperature condition not lower than 1100xc2x0 C., the upper portion of the side surface of the semiconductor layer can be easily rounded. If the CMP is effected on the upper portion of the side surface of the semiconductor layer to round the upper portion of the side surface of the semiconductor layer prior to the oxidation of the side surface of the semiconductor layer, the semiconductor device, which suppresses concentration of an electric field at the upper portion of the side surface of the semiconductor layer, can be easily formed. Further, the semiconductor layer and the insulating layer may be patterned to form the first insulating layer and the semiconductor layer located thereon as well as the second insulating layer spaced from the first insulating layer by a predetermined distance and the second semiconductor layer located thereon, the first nitride film may be formed in contact with the side surface of the first insulating layer and the lower portion of the side surface of the first semiconductor layer, the second nitride film may be formed in contact with the side surface of the second insulating layer and the lower portion of the side surface of the second semiconductor layer, and the oxide film may be formed to fill the area between the first and second nitride films. In this case, the oxide film reduces a difference in level, and a parasitic capacitance is also reduced.
According to a method of manufacturing a semiconductor device of a further aspect of the invention, a semiconductor layer, a first nitride film and an etching stopper layer are successively formed on an insulating layer. The etching stopper layer, the first nitride film, the semiconductor layer and the insulating layer are etched to have predetermined forms. A second nitride film is formed to cover the etching stopper layer, the first nitride film, the semiconductor layer and the insulating layer. The second nitride film is etched to leave a portion of the second nitride film being in contact with a side surface of the insulating layer and a lower portion of a side surface of the semiconductor layer.
Thereby, oxidant is prevented from moving to an area between the semiconductor layer and the insulating layer as well as an upper surface of the semiconductor layer when oxidizing the semiconductor layer. Thereby, only the side surface of the semiconductor layer is easily oxidized.
According to a method of manufacturing a semiconductor device of a further aspect of the invention, a semiconductor layer is formed on an insulating layer, and then the insulating layer and the semiconductor layer are patterned. Thereby, a first insulating layer and a first semiconductor layer located thereon as well as a second insulating layer spaced from the first insulating layer by a predetermined distance and a second semiconductor layer located thereon are formed. A nitride film is formed to fill a space between, on one hand, the first insulating layer and the first semiconductor layer and, on the other hand, the second insulating layer and the second semiconductor layer. The nitride film is etched back to leave a portion of the nitride film being in contact with side surfaces of the first and second insulating layers and lower portions of side surfaces of the first and second semiconductor layers.
Thereby, it is possible to prevent movement of oxidant to the lower surfaces of the first and second semiconductor layers when oxidizing the first and second semiconductor layers, and the nitride film reduces a difference in level between the first and second insulating layers.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.